C8051F063 查看數據表（PDF） - Silicon Laboratories

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C8051F063

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

VDD

VDD

VDD

DGND

DGND

DGND

AV+

AGND

TCK

TMS

TDI

TDO

/RST

MONEN

XTAL1

XTAL2

VREF

VREFD

DAC0

DAC1

AVDD

AGND

AV+

AGND

VREF0

VRGND0

AIN0

AIN0G

VBGAP

CNVSTR0

0

AV+

AGND

VVRRGENFD1

1

AIN1

AIN1G

VBGAP

CNVSTR1

1

Di gi tal Power

Analog Power

JT AG

Logic

Boundary Scan

Debug HW

VDDMonitor

WDT

8

0

5

1 Reset

External Osci l l ator

Circuit

T ri m m edInternal

Osci l l ator

VREF

DAC0

(12-Bi t)

C System Clock

o

r

e

SFR Bus

64kbyte

FLASH

32X136

CANRAM

256 byte

RAM

4kbyte RAM

ADC0

1Msps

(16-Bi t)

ADC1

1Msps

(16-Bi t)

External Data MemoryBus

A

D

C

0

D

A

T

A

+

D

Σ

I

F

A

F

D

-

C

1

DMA

Interface

EMIF

Control

D

A

T

A

UART 0

UART 1

SMBus

SPI Bus

PCA

Timers0, 1,

2,3,4

P0,P1,P2,

P3 Latches

CAN

2.0B

P0

Drv

C

P1

R

Drv

O

S

S

B

A

R

P2

Drv

P3

Drv

ADC2

200ksps

(10-Bit)

A

Temp

M

Sensor

U

X

CP0

+

-

P2.6

P2.7

CP1

+

-

P2.2

P2.3

CP2

+

-

P2.4

P2.5

P0.0

P0.7

P1.0/

AIN2.0

P1.7/

AIN2.7

P2.0

P2.7

P3.0

P3.7

CANTX

CANRX

VREF2

Bus Control

Address Bus

Data Bus

P4Latch

Ctrl Latch

P5Latch

Addr[15:8]

P6Latch

Addr[7:0]

P7Latch

Data Latch

P4

DRV

P5

DRV

P6

DRV

P7

DRV

P4.5

P4.6

P4.7

P5.0

P5.7

P6.0

P6.7

P7.0

P7.7

Figure 1.1. C8051F060 / C8051F062 Block Diagram

Rev. 1.2

21

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