EL4093C 查看數據表（PDF） - Elantec -> Intersil

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EL4093C

300 MHz DC restored video amplifier

Elantec -> Intersil 

EL4093C

300 MHz DC-Restored Video Amplifier

Applications Information Contd

Choice of Hold Capacitor

The EL4093 has been designed to work with a

hold capacitor of 2 2 nF With this value of

CHOLD the droop rate and hold step are negligi-

bly small for most applications In addition with

the special boost circuits inside the S H fast ac-

quisition is possible even using a hold capacitor

of this size Figure 5 below shows the input and

output of the DC-restored amplifier while the

S H is in sample mode Applying a a1V step to

the non-inverting input of the CFA the output

of the CFA jumps to a2V The S H however

then tries to autozero the system by driving the

CFA output back to the reference voltage Since

the input differential across the S H is initially

a2V the boost circuits turn on and supply

8 5 mA of charge current to the hold capacitor

The boost circuit remains on until the CFA out-

put has come to within 50 mV of the reference

Note that this event took only 320 ns settling to

within 1% of the final value takes another 2 ms

Thus for a 1V input step acquisition takes only

one to two NTSC scan lines

4093 – 41

Figure 5 Autozero Mechanism Restores

Amplifier Output to Ground

after a1V Step at Input

A natural question arises as to whether there are

other CHOLD values that can be used In one di-

rection increasing CHOLD will further reduce the

droop and hold step but lengthen the acquisition

time Since the droop and hold step are already

small to begin with there is no apparent advan-

tage to increasing CHOLD

In the other direction decreasing CHOLD would

increase the droop and hold step but shorten the

acquisition time There is however a caveat to

reducing CHOLD too small a CHOLD would

cause the autozero loop to oscillate The reason is

that when the S H boost circuit turns on the

input stage gm increases drastically and the cir-

cuit becomes nonlinear A sufficiently large

CHOLD must be used to suppress the non-lineari-

ty and force the loop to settle For example it

has been found that a CHOLD of 470 pF results in

1 VP-P oscillation around 10 MHz at the CFA

output

The minimum recommended value for CHOLD is

2 2 nF With this value the loop remains stable

over the entire operating temperature range

(b40 C to a85 C) The greatest instability oc-

curs at low temperatures where we observe from

the performance curves that the S H gm’s and

hence the GBWP are at their maximum If the

operating range is restricted to room temperature

or above then 1 5 nF is sufficient to keep the

loop stable At this value of CHOLD the acquisi-

tion time reduces to about 1 5 ms

Video Performance and Application

Although the EL4093 is intended for high speed

video applications such as SVGA it also offers

excellent performance for NTSC with 0 04% dG

and 0 02 dP at 3 58 MHz Some application con-

siderations however are required for handling

NTSC signals

Referring back to Figure 2 recall that typically

the autozero interval lies in the back porch por-

tion of video containing the colorburst pulse

When the S H compares the video to the refer-

ence voltage during this period the colorburst

(40 IREP-P) triggers the S H boost circuit and

prevents the autozero loop from settling

13

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