CM106-L 查看數據表（PDF） - C-Media Electronics
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CM106-L Datasheet PDF : 41 Pages
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CM106-F+/L+
High End 8CH DAC and 2CH ADC Integrated Solution
3.4 CM106-L+ LQFP 48 PIN DESCRIPTION
Pin # Symbol
1 PDSW
2
XI
3
XO
4 DVSS1
5 SDAT
6 SCLK
7
TEST
8 MCLK
9
MINT
10 GPIO1
11 LEDO
12 LEDR
13 PHONES
14
CS
15
SK
16
DR
17
DW
18 USBDP
19 USBDM
20 REGV
21 DVDD1
22 AVSS3
23 MICINL
Type
DO
DI
DO
P
DIO
DI
DI
DO
DO
DIO
DO
DO
DI
DO
DO
DO
DI
AIO
AIO
AO
P
P
AI
Description
Power down switch control (for PMOS polarity)
0: normal mode
1: power down mode
12MHz crystal, or oscillator input
12MHz crystal output
Digital ground
External MCU serial bus data pin
External MCU serial bus clock pin
Test mode select pin; pull low in normal operation
External MCU clock pin; clock frequency is programmable
(12MHz, 6MHz, 3MHz, 1.5MHz)
Default is 1.5 MHz
External MCU interrupt pin (active L)
When internal register address 0 ~ 3 or external serial EEPROM is
accessed,
MINT is set low; after MCU read, MINT is reset to H
GPIO pin #1
LED for operation; output H for power on; toggling for data transmit
LED for mute recording indication; output H when recording is muted
Phone jack sense pin for line out Tri-state; an internal register bit will be
set when activated (active H)
EEPROM interface chip select
EEPROM interface clock
EEPROM interface data read
EEPROM interface data write
USB data D+
USB data D-
3.3V reference output for internal 5 3.3V regulator
5V power supply to internal regulator
Analog ground
Microphone input left channel
Date: 08/19/2005
- 13 -
Version： 1.01
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