ILX526A 查看數據表（PDF） - Sony Semiconductor

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ILX526A

3000-pixel CCD Linear Image Sensor (B/W)

Sony Semiconductor 

φCLK-VOUT Timing ∗1

∗2

φCLK

ILX526A

t18

VOUT∗3

t19

VOUT

Item

Symbol

φCLK-VOUT output delay time1

t18

φCLK-VOUT output delay time2

t19

∗1 fck = 500kHz, φCLK Duty = 50%, φCLK rise/fall time = 10ns

∗2 is data period

∗3 Using internal sample-and-hold circuit

Min.

Typ.

Max. Unit

—

230

—

ns

—

210

—

ns

Application Circuit (Without S/H mode (Note))

5V

φCLK

φROG

φSHUT

1 Vgg

VDD 22

2 φCLK GND 21

3 NC

VOUT 20

4 NC

NC 19

5 NC

NC 18

6 φROG NC 17

7 φSHUT NC 16

8 GND

NC 15

9 VDD

VDD 14

10 T1

GND 13

11 NC S/HSW 12

0.01µ 22µ/10V

3kΩ

2SA1175

Note) This circuit diagram is the case when internal S/H is not used.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

–8–

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