GS8180D18D-333 查看數據表（PDF） - Giga Semiconductor

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GS8180D18D-333

18Mb Σ2x2B4 SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS8180D18D-333/300/250/200

C and C Controlled Read-Write-Read Timing Diagram

Read

Write

Read

Deselect

Read

Write Deselect

Write

Read

Write Deselect

K

K

A A1

A2

A3

A4

A5

A6

A7

A8

R

W

BWn

D

tKHCH

D20 D21 D22 D23

tKHCH

D50 D51 D52 D53 D60 D61 D62 D63 D80

C

tCHCH tCHCL tCLCH tCHCH tCHCH

C

tCHQV

tCHQX

tCHQV

tCHQX

tCHQZ

tCHQX1

Q10 Q11 Q12 Q13 Q30 Q31 Q32 Q33 Q40 Q41 Q42 Q43

Q70

Q

tCHCQH

CQ

tCHCQH

tCQHQX

tCQHQV

tCQHQX

tCQHQV

CQ

tCQHCQL1

tCQLCQH1

Rev: 2.00f 6/2002

20/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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