GS8180D18D-333 查看數據表（PDF） - Giga Semiconductor

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GS8180D18D-333

18Mb Σ2x2B4 SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS8180D18D-333/300/250/200

JTAG TAP Instruction Set Summary

Instruction Code

Description

EXTEST

000 Places the Boundary Scan Register between TDI and TDO.

IDCODE

001 Preloads ID Register and places it between TDI and TDO.

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Forces all RAM output drivers to High-Z.

RFU

011 Do not use this instruction; Reserved for Future Use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

RFU

101 Do not use this instruction; Reserved for Future Use.

RFU

110 Do not use this instruction; Reserved for Future Use.

BYPASS

111 Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Notes

1

1, 2

1

1

1

1

1

1

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

Test Port Input High Voltage

VIHJ

0.6 * VDD

VDD +0.3

V

1

Test Port Input Low Voltage

VILJ

–0.3

0.3 * VDD

V

1

TMS, TCK and TDI Input Leakage Current

IINHJ

–300

1

uA

2

TMS, TCK and TDI Input Leakage Current

IINLJ

–1

100

uA

3

TDO Output Leakage Current

IOLJ

–1

1

uA

4

Test Port Output High Voltage

VOHJ

VDD – 400 mV

—

V 5, 6

Test Port Output Low Voltage

VOLJ

—

0.4

V 5, 7

Test Port Output CMOS High

VOHJC

VDD – 100 mV

—

V 5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V not to exceed 2.6 V maximum, with a pulse width not to

exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDD

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDD

5. The TDO output driver is served by the VDD supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

Rev: 2.00f 6/2002

25/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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