GS8180D18D-333I 查看數據表（PDF） - Giga Semiconductor

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GS8180D18D-333I

18Mb Σ2x2B4 SigmaQuad SRAM

Giga Semiconductor 

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

VDD

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDD/2

Output reference level

VDD/2

Notes:

1. Distributed scope and test jig capacitance.

2. Test conditions as shown unless otherwise noted.

Preliminary

GS8180D18D-333/300/250/200

JTAG Port AC Test Load

DQ

50Ω

30pF*

VT = VDD/2

* Distributed Test Jig Capacitance

JTAG Port Timing Diagram

tTKH

tTKL

tTKC

TCK

tTS tTH

TMS

TDI

TDO

JTAG Port AC Electrical Characteristics

Parameter

TCK Cycle Time

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

tTKQ

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

tTH

Min.

Max

Unit

50

—

ns

—

20

ns

20

—

ns

20

—

ns

10

—

ns

10

—

ns

Rev: 2.00f 6/2002

26/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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