CMX881 查看數據表（PDF） - CML Microsystems Plc

零件编号

产品描述 (功能)

生产厂家

CMX881

Baseband Processor for PMR and Trunked Radios

CML Microsystems Plc 

PMR Signalling Processor

CMX881

1.5.3.5 Receiving FFSK Signals

The CMX881 can decode incoming FFSK/MSK signals at either 1200 or 2400 baud data rates. It can

achieve this by deriving the baud rate from the received signal. Alternatively a control word may set the

baud rate, in which case the device only responds to signals operating at that rate. The form of

FFSK/MSK signals for these baud rates, excluding noise, is shown in Figure 11.

The received signal is filtered and data is extracted. A PLL is used to extract the clock from the

recovered serial data stream. The recovered data is stored in a 1 byte buffer and an interrupt issued to

indicate received data is ready. Data is transferred over the C-BUS, controlled by host instructions. If

this data is not read before the next data is decoded it will be overwritten. The MSK bit clock is not

output externally. It is up to the user to ensure that the data is transferred at an adequate rate following

data ready being flagged, see Table 9.

The extracted data is compared with up to three 16-bit programmed frame sync patterns (SYND, SYNC

and it's inverse SYNT). SYNC and SYND are both preset to $C4D7 following a RESET command. An

interrupt will be flagged when the programmed frame sync pattern is detected. The host may stop the

frame sync search by disabling the MSK demodulator.

FFSK may be transmitted in conjunction with a CTCSS or DCS sub-audio component. The device will

handle the sub-audio signals as already described. If a sub-audio signal turns off during reception of

FFSK, it is up to the host µC to turn off the FFSK decoding as the device will continue receiving and

processing the incoming signal until commanded otherwise by the host µC.

The host must keep track of the message length or otherwise determine the end of reception (e.g. by

using sub-audio information or the Auxiliary ADC to check for signal level) and disable the FFSK

demodulator at the appropriate time.

 2004 CML Microsystems Plc

21

D/881/7

Share Link: