VL-FS-COG-VLGT6566-04 查看數據表（PDF） - Varitronix international limited
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VL-FS-COG-VLGT6566-04 Datasheet PDF : 18 Pages
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3. Interface signals
VL-FS-COG-VLGT6566-04 REV.B
(COG-VLGT6566-04)
OCT/2010
PAGE 8 OF 18
Pin No.
1~2
3~4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Table 2(a): Pin assignment
Symbol
Description
VSS
Ground.
VDD
(VDDIO,VCI)
Power supply.
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
Digital data input.
G4
R7~R0/G7~G0/B7~B0 are used.
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
VSS
Ground.
PCLK
(CLK/DOTCLK)
Clock signal for data latching in RGB interface.
Display on/off mode control. Internally pulled high.
PON (DISP) (a) DISP=L, standby mode.
(b) DISP=H, normal display mode.
HSYNC
(HS)
Horizontal sync input in RGB interface.
VSYNC
(VS)
Vertical sync input in RGB interface.
DE
Input data enable control in RGB interface.
NC
No connection.
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