CP2120 查看數據表（PDF） - Silicon Laboratories

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CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

CP2120

6. I2C Serial Interface

The CP2120 provides an I2C interface able to transfer data at frequencies up to 400 kHz. During a transaction, the

CP2120, operating as the I2C master, sources a data clock on the SCL pin as data travels across the bidirectional

SDA pin to and from an I2C slave device. The I2C interface lines each require a pull-up resistor. Figure 5 shows a

typical I2C bus.

VDD

RpU

RpU

I²C-bus

SDA

SCL

CP2120

I²C-BUS Device

I²C-BUS DEVICE

Figure 5. Typical I2C Bus*

Note: VDD is defined in Table 2, “Absolute Maximum Ratings,” on page 4. For Rpu values, please see “6.1. Determining Pull-

Up Register Values” .

Note: The I2C interface does not currently support repeated start transactions, as required by some I2C slave devices.

6.1. Determining Pull-Up Register Values

Logic low to logic high transitions on the SCL and SDA pins, which are configured to open-drain output with

external pull-ups to VDD, take the form of

capacitance of the bus and R equals the

an exponential

pull-up resistor

curve with

value. I2C

an RC time constant, where C equals the

specification defines rise time as the time

required for a signal level to change from Vmin +0.15 V to Vmax-0.15 V. By solving the exponential equation using

a Vmin of 0 V and a Vmax of 3.3 V, the following equation can be used to find values for pull-up resistors:

Rise time = 3.04448 RC

Bus capacitance is governed by a number of factors, including signal trace length and capacitance introduced by

devices on the bus. 8 mm PCB signal traces on a two-layer board generally add 1 pF of capacitance per

centimeter of trace length. To determine the amount of capacitance introduced to the bus by I2C devices, consult

those devices’ datasheets. The maximum capacitance allowed before the bus violates I2C specification is 400 pF.

Rise time requirements vary depending on each connected I2C device’s timing requirements and the SCL clock

frequency. The maximum rise time allowed by the I2C specification is 1000 ns.

6.2. I2C Internal Registers

Features of the I2C interface are configured through the CP2120's Internal Registers. SCL clock frequency is set

by writing to the I2CCLK Internal Register. The frequency can be determined using the equation below. The I2C

frequency configured by the I2CCLOCK register is only an approximate frequency. Actual I2C frequencies can vary

due to conditions on the bus, such as a slave device extending the SCL low time.

I2C Clock Frequency (kHz)

=

-----2---0---0----0------

I2CCLK

Equation 1. I2C Clock Frequency

Rev. 1.0

13

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