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CS4811MXR-01 查看數據表(PDF) - Cirrus Logic

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CS4811MXR-01 Datasheet PDF : 24 Pages
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CS4811
2. TYPICAL CONNECTION DIAGRAMS
Ferrite Bead
+ 1 µF 0.1 µF
+ 1 µF 0.1 µF
A
A
D
D
150
+
22 µF
86
2.2 nF
12 18 88
VA 1..3
AIN+
A
+
100 µF
87 AIN -
0.1 µF
A
A
65 43
VD 1..2
AOUT + 7
AOUT - 8
+5 V Supply
ANALOG
FILTER
39
OVL
To Optional
Input and 1 µF
Output Buffers
+ 1 µF
92
CMOUT
0.1 µF
AA
93
0.1 µF
94
CMFILT+
CMFILT-
A
VD VD
2.2 K
2.2 K
Serial EEPROM
63 SCL/CCLK
62 SDA/CDOUT
68 AD0/CS
67 AD1/CDIN
CS4811
VD
RES-VD 70, 73
9, 10, 14, 15, 16, 17, 20
RES-NC
21, 22, 23, 47, 57, 58, 59
RES-NC
60, 61, 71, 95, 97, 90, 91
RES-NC
Mode/Reset
Circuit
RESET
Control/
Monitor
Circuitry
69 SPI/I2C
72 RST
41
PIO0
40
PIO1
37
PIO2
35
PIO3
AGND1..4 DGND1..4
11 13 19 89 42 44 64 66
RS = 33
A
D
All unused inputs
should be tied to ground.
32, 36, 38, 48, 96, 82, 83
RES-DGND
1, 2, 3, 4, 5, 6
RES-DGND
24, 25, 26, 27, 28, 29, 30
RES-DGND
31, 33, 49, 50, 51, 52, 53
RES-DGND
54, 55, 56, 74, 75, 76, 77
RES-DGND
78, 79, 80, 81, 84, 85, 98, 99, 100
RES-DGND
D
XTO XTI
46 45
1 M
39 pF 39 pF
D
D
Caps, Xtal, and
resistor not needed
with external clock
input to XTI.
Figure 3. Typical Connection Diagram, Single-ended Input
10
DS486PP2

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