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CS5102A(1995) 查看數據表(PDF) - Cirrus Logic

零件编号
产品描述 (功能)
生产厂家
CS5102A
(Rev.:1995)
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS5102A Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CS5102A
ANALOG CHARACTERISTICS (continued)
CS5102A -J,K CS5102A -A,B
Parameter*
Symbol Min Typ Max Min Typ Max
Specified Temperature Range
-
0 to +70
40 to +85
Analog Input
Aperture Time
Aperture Jitter
-
- 30 - - 30 -
-
- 100 - - 100 -
Input Capacitance
(Note 6)
Unipolar Mode
Bipolar Mode
Conversion & Throughput
Conversion Time
(Note 19)
Acquisition Time
(Note 20)
Throughput
(Note 21)
Power Supplies
Power Supply Current
(Note 22)
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
Power Consumption
(Notes 11, 22)
(SLEEP High)
(SLEEP Low)
Power Supply Rejection:
(Note 23)
Positive Supplies
Negative Supplies
-
-
tc
ta
ftp
IA+
IA-
ID+
ID-
Pdo
Pds
PSR
PSR
- 320 425 - 320 425
- 200 265 - 200 265
- - 40.625 - - 40.625
- - 9.375 - - 9.375
20 - - 20 - -
- 2.4 3.5 - 2.4 3.5
- -2.4 -3.5 - -2.4 -3.5
- 2.5 3.5 - 2.5 3.5
- -1.5 -2.5 - -1.5 -2.5
- 44 65 - 44 65
-1- -1-
- 84 -
- 84 -
- 84 -
- 84 -
Units
°C
ns
ps
pF
pF
µs
µs
kHz
mA
mA
mA
mA
mW
mW
dB
dB
Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling
edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will
not exceed 1 master clock cycle + 140 ns.
20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with an 1.6 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may
be less than 9 clock cycles.
21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.
23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rejection versus frequency.
Typ. Power (mW) CLKIN (MHz)
34
0.8
37
1.0
39
1.2
41
1.4
44
1.6
6
DS45F2

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