CXD4016R 查看數據表（PDF） - Sony Semiconductor

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CXD4016R

Transmission Digital Signal Processor IC for Infrared Spatial Digital Audio Communication

Sony Semiconductor 

CXD4016R

Description of Functions

Description of clock generator

1. This LSI chip can generate the system clock pulse by connecting a 24.576MHz crystal oscillator to the OSCI

pin and OSCO pin. Also, it incorporates 1MΩ (typ.) feedback resistor between the OSCI and OSCO pins.

2. It functions as the system clock by inputting a 24.576MHz external oscillation clock pulse to the OSCI pin

while keeping the OSCO pin open.

3. Please keep the frequency precision for system clock within 24.576MHz ± 100ppm.

Description of PLL circuit

1. In addition to supplying the system clock pulse using the OSCI pin, this LSI requires the modulation clock

pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this

purpose.

2. If the sampling frequency of the digital audio input signals is fs, then the modulation clock pulse provided

by the PLL circuit has a frequency of 640fs.

3. When the PLL circuit on the LSI is used, input a low level to the EXCKSEL pin and VCOT pin. Furthermore,

an external lag-lead filter must be connected to the LSI for the charge pump current output APCPO pin of

the PLL circuit. Ensure that the wiring involved is kept as short as possible.

4. When the PLL circuit on the LSI is not used, the LSI chip must be provided with an external PLL circuit.

Input a high level to the EXCKSEL pin and the modulation clock pulse to the VCOT pin. The reference

signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set

to fs. At this time, the frequency of the clock pulse which has been input to the VCOT pin is divided by 640

inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin.

Pin setting/serial data interface

The setting modes of this LSI can be broadly classified into two : the pin setting mode and the serial data

interface mode. By setting serial data interface mode, switching between pin setting mode and serial data

interface mode is enabled. For example, setting SCEN01 bit to “0” validate pin setting mode and setting it to

“1” validate serial data interface setting mode during Address 01 in serial data interface mode. (See “(3) Serial

setting command table” on the next page.) Followings are pins which can be set even in the serial data

interface mode.

EXCKSEL pin, DIVCODE pin, CHNM_BL pin, IFEXMD pin, IIFSEL1 pin, IIFSEL0 pin, PCMID pin, EMPIN pin.

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