HM62V256 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HM62V256

32,768-word × 8-bit Low Voltage Operation CMOS Static RAM

Hitachi -> Renesas Electronics 

HM62V256 Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol Min Typ*1 Max Unit Test conditions*6

VCC for data retention

Data retention current

VDR

ICCDR

2.0 — 3.6 V

CS ≥ VCC – 0.2 V, Vin ≥ 0 V

—

0.05 27*2 µA VCC = 2.7 V, Vin ≥ 0 V

CS ≥ VCC – 0.2 V

—

0.05 7*3

—

0.05 2*4

Chip deselect to data retention time tCDR

0

— — ns See retention waveform

Operation recovery time

tR

t *5

RC

—

—

ns

Notes: 1. Typical values are at VCC = 2.7 V, Ta = 25°C and not guaranteed.

2. 9 µA max at Ta = 0 to 40°C.

3. This characteristics guaranteed for only L-SL version. 2.0 µA max at Ta = 0 to 40°C.

4. This characteristics guaranteed for only L-UL version. 0.4 µA max at Ta = 0 to 40°C.

5. tRC = read cycle time.

6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention

mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.

Low VCC Data Retention Timing Waveform

VCC

2.7 V

0.7 VCC

VDR

CS

0V

t CDR

Data retention mode

tR

CS > VCC – 0.2 V

12

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