CY7C1049CV33-10VXA 查看數據表（PDF） - Cypress Semiconductor

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CY7C1049CV33-10VXA

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049CV33 Automotive

Switching Waveforms

Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12]

tRRCC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]

ADDRESS

CE

OE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15]

ADDRESS

CE

tWC

tSCE

tAW

tHA

tSA

tPWE

WE

OE

DATA I/O

NOTE 16

tSD

tHD

DATA VALID

tHZOE

Notes

11. Device is continuously selected. OE, CE = VIL.

12. WE is HIGH for read cycles.

13. Address valid before or similar to CE transition LOW.

14. Data I/O is high impedance if OE = VIH.

15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

16. During this period, the I/Os are in output state. Do not apply input signals.

Document #: 001-67511 Rev. **

Page 7 of 13

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