80960CF-40(2002) 查看數據表（PDF） - Intel

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80960CF-40
(Rev.:2002)

32-Bit High-Performance Superscalar Embedded Microprocessor

Intel 

80960-40, -33, -25

Figure 19. ICC vs. Frequency and Temperature—80960CF-40

1100

TC = 1000°

TC = 85° C

ICC - ICC under test conditions

0

0

fPCLK (MHz)

40

F_CX020A

5.0

Reset, Backoff and Hold Acknowledge

Table 20 lists the condition of each processor output pin while RESET is asserted (low). Table 21

lists the condition of each processor output pin while HOLDA is asserted (high).

In Table 21, with regard to bus output pin state only, the Hold Acknowledge state takes precedence

over the reset state. Although asserting the RESET pin internally resets the processor, the

processor’s bus output pins do not enter the reset state when Hold Acknowledge has been granted

to a previous HOLD request (HOLDA is active). Furthermore, the processor grants new HOLD

requests and enters the Hold Acknowledge state even while in reset.

For example, when HOLD is asserted while HOLDA is inactive and the processor is in the reset

state, the processor’s bus pins enter the Hold Acknowledge state and HOLDA is granted. The

processor is not able to perform memory accesses until the HOLD request is removed, even when

the RESET pin is brought high. This operation is provided to simplify boot-up synchronization

among multiple processors sharing the same bus.

Datasheet

41

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