HM62256BLFP-4SLT 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HM62256BLFP-4SLT

32,768-word × 8-bit High Speed CMOS Static RAM

Hitachi -> Renesas Electronics 

HM62256B Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol Min Typ*1 Max

Unit

Test Conditions*6

VCC for data retention

VDR

2.0 —

5.5

V

CS ≥ VCC –0.2 V,

Vin ≥ 0 V

Data retention current

I CCDR

— 0.05

30*2

µA

— 0.05

10*3

— 0.05

3*4

VCC = 3.0 V, Vin ≥ 0 V

CS ≥ VCC –0.2 V,

Chip deselect to data retention time tCDR

0

—

—

ns

See retention waveform

Operation recovery time

tR

t *5

RC

—

—

ns

Notes: 1. Typical values are at VCC = 3.0 V, Ta = 25°C and not guaranteed.

2. 10 µA max at Ta = 0 to + 40°C.

3. This characteristics guaranteed for only L-SL version. 3 µA max at Ta = 0 to +40°C.

4. This characteristics guaranteed for only L-UL version. 0.6 µA max at Ta = 0 to +40°C.

5. tRC = read cycle time.

6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data

retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.

Low VCC Data Retention Timing Waveform

VCC

4.5V

2.2V

VDR

CS

0V

t

CDR

Data retention mode

tR

CS > VCC - 0.2V

13

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