CY8C20524 查看數據表（PDF） - Cypress Semiconductor

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CY8C20524

CapSense® PSoC® Programmable System-on-Chip™

Cypress Semiconductor 

32-pin Part Pinout

CY8C20224, CY8C20324

CY8C20424, CY8C20524

Figure 6. CY8C20424 32-pin PSoC Device

AI, P0[1] 1

AI, P2[7] 2

AI, P2[5] 3

AI, P2[3] 4

AI, P2[1] 5

AI, P3[3] 6

AI, P3[1] 7

SPI SS, P1[7] 8

AI, I2C SC L

QFN

(Top View )

24 P0[0], AI

23 P2[6], AI

22 P2[4], AI

21 P2[2], AI

20 P2[0], AI

19 P3[2], AI

18 P3[0], AI

17 XRES

Table 4. 32-pin Part Pinout (QFN [5])

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Digital Analog

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

IOH

I

IOH

I

IOH

I

IOH

I

Power

IOH

I

IOH

I

IOH

I

IOH

I

Input

I/O

I

I/O

I

I/O

I

I/O

I

Name

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

P3[1]

P1[7]

P1[5]

P1[3]

P1[1]

VSS

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P3[0]

P3[2]

P2[0]

P2[2]

Integrating Input

Description

I2C SCL, SPI SS

I2C SDA, SPI MISO

SPI CLK

CLK[6], I2C SCL, SPI MOSI

Ground connection

DATA[6], I2C SDA

Optional external clock input (EXTCLK)

Active high external reset with internal pull-down

Notes

5. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically

floated and not connected to any other signal.

6. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Document Number: 001-41947 Rev. *L

Page 10 of 41

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