CY8C3666AXI-031 查看數據表（PDF） - Cypress Semiconductor

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CY8C3666AXI-031

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®3: CY8C36 Family Data Sheet

Figure 1-1 illustrates the major components of the CY8C36

family. They are:

„ 8051 CPU Subsystem

„ Nonvolatile Subsystem

„ Programming, Debug, and Test Subsystem

„ Inputs and Outputs

„ Clocking

„ Power

„ Digital Subsystem

„ Analog Subsystem

PSoC’s digital subsystem provides half of its unique config-

urability. It connects a digital signal from any peripheral to any

pin through the Digital System Interconnect (DSI). It also

provides functional flexibility through an array of small, fast, low

power Universal Digital Blocks (UDBs). PSoC Creator provides

a library of pre-built and tested standard digital peripherals

(UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR,

and so on) that are mapped to the UDB array. The designer can

also easily create a digital circuit using boolean primitives by

means of graphical design entry. Each UDB contains Program-

mable Array Logic (PAL)/Programmable Logic Device (PLD)

functionality, together with a small state machine engine to

support a wide variety of peripherals.

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C36 family these blocks can include four 16-bit timer,

counter, and PWM blocks; I2C slave, master, and multi-master;

Full-Speed USB; and Full CAN 2.0b.

For more details on the peripherals see the “Example Periph-

erals” section on page 35 of this data sheet. For information on

UDBs, DSI, and other digital blocks, see the “Digital Subsystem”

section on page 35 of this data sheet.

PSoC’s analog subsystem is the second half of its unique config-

urability. All analog performance is based on a highly accurate

absolute voltage reference with less than 0.9% error over

temperature and voltage. The configurable analog subsystem

includes:

„ Analog muxes

„ Comparators

„ Voltage references

„ Analog-to-Digital Converter (ADC)

„ Digital-to-Analog Converters (DACs)

„ Digital Filter Block (DFB)

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals. The heart of the analog

subsystem is a fast, accurate, configurable Delta-Sigma ADC

with these features:

„ Less than 100 µV offset

„ A gain error of 0.2%

„ Integral Non Linearity (INL) less than 1 LSB

„ Differential Non Linearity (DNL) less than 1 LSB

„ Signal-to-noise ratio (SNR) better than 70 dB (Delta-Sigma) in

12-bit mode

This converter addresses a wide variety of precision analog

applications including some of the most demanding sensors.

The output of the ADC can optionally feed the programmable

DFB via Direct Memory Access (DMA) without CPU intervention.

The designer can configure the DFB to perform IIR and FIR

digital filters and several user defined custom functions. The

DFB can implement filters with up to 64 taps. It can perform a

48-bit multiply-accumulate (MAC) operation in one clock cycle.

Four high speed voltage or current DACs support 8-bit output

signals at update rate of 8 Msps in current DAC (IDAC) and 1

Msps in voltage DAC (VDAC). They can be routed out of any

GPIO pin. You can create higher resolution voltage PWM DAC

outputs using the UDB array. This can be used to create a pulse

width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz.

The digital DACs in each UDB support PWM, PRS, or

delta-sigma algorithms with programmable widths.

In addition to the ADC, DACs, and DFB, the analog subsystem

provides multiple:

„ Uncommitted opamps

„ Configurable Switched Capacitor/Continuous Time (SC/CT)

blocks. These support:

‡ Transimpedance amplifiers

‡ Programmable gain amplifiers

‡ Mixers

‡ Other similar analog components

See the “Analog Subsystem” section on page 48 of this data

sheet for more details.

PSoC’s 8051 CPU subsystem is built around a single cycle

pipelined 8051 8-bit processor running up to 67 MHz. The CPU

subsystem includes a programmable nested vector interrupt

controller, DMA controller, and RAM. PSoC’s nested vector

interrupt controller provides low latency by allowing the CPU to

vector directly to the first address of the interrupt service routine,

bypassing the jump instruction required by other architectures.

The DMA controller enables peripherals to exchange data

without CPU involvement. This allows the CPU to run slower

(saving power) or use those CPU cycles to improve the perfor-

mance of firmware algorithms. The single cycle 8051 CPU runs

ten times faster than a standard 8051 processor. The processor

speed itself is configurable allowing active power consumption

to be tuned for specific applications.

Document Number: 001-53413 Rev. *B

Page 4 of 99

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