CY8C3666AXI-031 查看數據表（PDF） - Cypress Semiconductor

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CY8C3666AXI-031

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®3: CY8C36 Family Data Sheet

Figure 2-1. 48-Pin SSOP Part Pinout

(SIO) P12[2] 1

(SIO) P12[3] 2

(OpAmp2out, GPIO) P0[0] 3

(OpAmp0out, GPIO) P0[1] 4

(OpAmp0+, GPIO) P0[2] 5

(OpAmp0-/Extref0, GPIO) P0[3] 6

Vddio0 7

(OpAmp2+, GPIO) P0[4] 8

(OpAmp2-, GPIO) P0[5] 9

(IDAC0, GPIO) P0[6] 10

(IDAC2, GPIO) P0[7] 11

Vccd 12

Vssd 13

Vddd 14

(GPIO) P2[3] 15

(GPIO) P2[4] 16

Vddio2 17

(GPIO) P2[5] 18

(GPIO) P2[6] 19

(GPIO) P2[7] 20

Vssb 21

Ind 22

Vboost 23

Vbat 24

48 Vdda

47 Vssa

Lines show 46 Vcca

Vddio to IO

supply

45

P15[3] (GPIO, kHz XTAL: Xi)

association 44 P15[2] (GPIO, kHz XTAL: Xo)

43 P12[1] (SIO, I2C1: SDA)

42 P12[0] (SIO, I2C1: SCL)

41 Vddio3

40 P15[1] (GPIO, MHz XTAL: Xi)

39 P15[0] (GPIO, MHz XTAL: Xo)

38 Vccd

SSOP

37 Vssd

36 Vddd

35 P15[7] (USBIO, D-, SWDCK) [2]

34 P15[6] (USBIO, D+, SWDIO) [2]

33 P1[7] (GPIO)

32 P1[6] (GPIO)

31 Vddio1

30 P1[5] (GPIO, nTRST)

29 P1[4] (GPIO, TDI)

28 P1[3] (GPIO, TDO, SWV)

27 P1[2] (GPIO, configurable XRES)

26 P1[1] (GPIO, TCK, SWDCK)

25 P1[0] (GPIO, TMS, SWDIO)

Figure 2-2. 48-Pin QFN Part Pinout[4]

(GPIO) P2[6] 1

(GPIO) P2[7] 2

Vssb 3

Ind 4

Vb 5

Vbat 6

(GPIO, TMS, SWDIO) P1[0] 7

(GPIO, TCK, SWDCK) P1[1] 8

(GPIO, Configurable XRES) P1[2] 9

(GPIO, TDO, SWV) P1[3] 10

(GPIO, TDI) P1[4] 11

(GPIO, nTRST) P1[5] 12

Lines show

Vddio to I/O

supply

association

QFN

( Top View)

36 P0[3] (OpAmp0-/Extref0, GPIO)

35 P0[2] (OpAmp0+, GPIO)

34 P0[1] (OpAmp0out, GPIO)

33 P0[0] (OpAmp2out, GPIO)

32 P12[3] (SIO)

31 P12[2] (SIO)

30 Vdda

29 Vssa

28 Vcca

27 P15[3] (GPIO, kHz XTAL: Xi)

26 P15[2] (GPIO, kHz XTAL: Xo)

25 P12[1] (SIO, I2C1: SDA)

Document Number: 001-53413 Rev. *B

Page 6 of 99

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