CY8C38 查看數據表（PDF） - Cypress Semiconductor
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CY8C38 Datasheet PDF : 100 Pages
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PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
1. Architectural Overview
Introducing the CY8C38 family of ultra low power, Flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC®5 platform. The CY8C38 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a very flexible analog subsystem, digital subsystem, routing, and I/O
enables a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
4- 33 MHz
( Optiona)l
32.768 KHz
( Optiona)l
SYSTEM WIDE
RESOURCES
Xtal
Osc
IMO
RTC
Timer
WDT
and
Wake
ILO
Clocking System
Power Management
System
POR and
LVD
Sleep
Power
1.8V LDO
SMP
Digital Interconnect
Analog Interconnect
DIGITAL SYSTEM
Universal Digital Block Array (24x UDB)
8- Bit Quadrature Decoder
Timer
16- Bit 16- Bit PRS
PWM
UDB
UDB
UDB
UDB
UDB
UDB
CAN
2.0
UDB
I2C Slave
UDB
UDB
8- Bit SPI
UDB
UDB
UART
UDB
UDB
12- Bit SPI
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
Logic
UDB
12- Bit PWM
UDB
UDB
UDB
UDB
UDB
4x
Timer
Counter
PWM
I2C
Master/
Slave
FS USB
2.0
SYSTEM BUS
MEMORY SYSTEM
EEPROM
SRAM
CPU SYSTEM
8051 or
Cortex M3 CPU
Interrupt
Controller
EMIF
FLASH
PHUB
DMA
Program &
Debug
Program
Debug &
Trace
Boundary
Scan
LCD Direct
Drive
Digital
Filter
Block
4 x SC/ CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
CapSense
4 x DAC
ANALOG SYSTEM
ADC
1x
Del Sig
ADC
+
4x
Opamp
-
+
4x
CMP
-
USB
D+
PHY
D-
3 per
Opamp
0. 5 to5.5V
( Optiona)l
Document Number: 001-11729 Rev. *I
Page 3 of 100
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