CY8C5488LTI-037 查看數據表（PDF） - Cypress Semiconductor

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CY8C5488LTI-037

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®5: CY8C54 Family Data Sheet

SIOs are in input mode they are high impedance. This is true

even when the device is not powered or when the pin voltage

goes above the supply voltage. This makes the SIO ideally suited

for use on an I2C bus where the PSoC may not be powered when

other devices on the bus are. The SIO pins also have high

current sink capability for applications such as LED drives. The

programmable input threshold feature of the SIO can be used to

make the SIO function as a general purpose analog comparator.

For devices with Full-Speed USB the USB physical interface is

also provided (USBIO). When not using USB these pins may

also be used for limited digital functionality and device

programming. All the features of the PSoC I/Os are covered in

detail in the “I/O System and Routing” section on page 26 of this

data sheet.

The PSoC device incorporates flexible internal clock generators,

designed for high stability, and factory trimmed for absolute

accuracy. The Internal Main Oscillator (IMO) is the master clock

base for the system with 1% absolute accuracy at 3 MHz. The

IMO can be configured to run from 3 MHz up to 72 MHz. Multiple

clock derivatives can be generated from the main clock

frequency to meet application needs. The device provides a PLL

to generate system clock frequencies up to 79 MHz (80 MHz

including +1% tolerance) from the IMO, external crystal, or

external reference clock. It also contains a separate, very low

power Internal Low Speed Oscillator (ILO) for the sleep and

watchdog timers. A 32.768 kHz external watch crystal is also

supported for use in Real Time Clock (RTC) applications. The

clocks, together with programmable clock dividers, provide the

flexibility to integrate most timing requirements.

The CY8C54 family supports a wide supply operating range from

1.71 to 5.5V. This allows operation from regulated supplies such

as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly

from a wide range of battery types. In addition, it provides an

integrated high efficiency synchronous boost converter that can

power the device from supply voltages as low as 0.5V. This

enables the device to be powered directly from a single battery

or solar cell. In addition, the designer can use the boost converter

to generate other voltages required by the device, such as a 3.3V

supply for LCD glass drive. The boost’s output is available on the

Vboost pin, allowing other devices in the application to be

powered from the PSoC.

PSoC supports a wide range of low power modes. These include

a 300 nA hibernate mode with RAM retention and a 2 µA sleep

mode with real time clock (RTC). In the second mode the

optional 32.768 kHz watch crystal runs continuously and

maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 2 mA when the CPU is running at

6 MHz.

The details of the PSoC power modes are covered in the “Power

System” section on page 22 of this data sheet.

PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)

interfaces for programming, debug, and test. Using these

standard interfaces enables the designer to debug or program

the PSoC with a variety of hardware solutions from Cypress or

third party vendors. The Cortex-M3 debug and trace modules

include Flash Patch and Breakpoint (FPB), Data Watchpoint and

Trace (DWT), Embedded Trace Macrocell (ETM), and Instru-

mentation Trace Macrocell (ITM). These modules have many

features to help solve difficult debug and trace problems. Details

of the programming, test, and debugging interfaces are

discussed in the “Programming, Debug Interfaces, Resources”

section on page 54 of this data sheet.

2. Pinouts

The Vddio pin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1

through Figure 2-3. Using the Vddio pins, a single PSoC can

support multiple interface voltage levels, eliminating the need for

off-chip level shifters. Each Vddio may sink up to 100 mA total to

its associated I/O pins and opamps. On the 68 pin and 100 pin

devices each set of Vddio associated pins may sink up to 100

mA. The 48 pin device may sink up to 100 mA total for all Vddio0

plus Vddio2 associated I/O pins and 100 mA total for all Vddio1

plus Vddio3 associated I/O pins.

Document Number: 001-55036 Rev. *A

Page 5 of 93

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