CYRF6936 查看數據表（PDF） - Cypress Semiconductor
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CYRF6936 Datasheet PDF : 28 Pages
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CYRF6936
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS pin is LOW. When using this configuration,
user firmware must ensure that the MOSI pin on the MCU is in a
high impedance state whenever the SS pin is HIGH.
Table 3. SPI Transaction Format
Parameter
Bit #
7
6
Bit Name
DIR
INC
Byte 1
[5:0]
Address
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VI/O). This enables the device to interface
directly to MCUs operating at voltages below the CYRF6936 IC
supply voltage.
Byte 1+N
[7:0]
Data
Figure 4. SPI Single Read Sequence
SCK
SS
MOSI
MISO
cmd
addr
DIR
0
INC
A5
A4
A3
A2
A1
A0
data to mcu
D7 D6 D5 D4 D3 D2 D1 D0
SCK
SS
MOSI
MISO
Figure 5. SPI Incrementing Burst Read Sequence
cmd
addr
DIR
0
INC
A5
A4
A3
A2
A1
A0
data to mcu1
data to mcu1+N
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. SPI Single Write Sequence
SCK
SS
MOSI
MISO
SCK
SS
MOSI
MISO
cmd
addr
data from mcu
DIR
1
INC
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7. SPI Incrementing Burst Write Sequence
cmd
addr
data from mcu1
data from mcu1+N
DIR
1
INC
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Document #: 38-16015 Rev. *J
Page 7 of 28
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