DS1721S-T,R 查看數據表（PDF） - Maxim Integrated

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DS1721S-T,R

2-Wire Digital Thermometer and Thermostat

Maxim Integrated 

Capacitive Load for

each Bus Line

Cb

Input Capacitance

CI

NOTES:

1. All voltages are referenced to ground.

400

pF

5

pF

DS1721

8

2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.

3. IDD specified with TOUT pin open.

4. IDD specified with VDD at 5.0V and SDA,SCL = 5.0V, 0°C to 70°C.

5. After this period, the first clock pulse is generated.

6. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

7. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT >250 ns must

then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tR MAX+tSU:DAT 1000+250 = 1250 ns before the SCL line is released.

8. Cb - total capacitance of one bus line in pF.

TIMING DIAGRAMS Figure 7

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