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DS1722S/TR 查看數據表(PDF) - Maxim Integrated

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DS1722S/TR Datasheet PDF : 14 Pages
First Prev 11 12 13 14
TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 12
DS1722
*SCLK can be either polarity, timing shown for CPOL = 1.
NOTES:
1. All voltages are referenced to ground.
2. Logic 0 voltages are specified at a sink current of 3 mA.
3. Logic 1 voltages are specified at a source current of 1 mA.
4. ICC specified with SCLK=VDDD and CE=GND. Typical ICC1 is 0.25 µA and ICC is 0.3 mA at 25°C
and VDDD = 2.65V.
5. Measured at VIH =0.7 VDDD or VIL=0.2 VDDD and 10 ms maximum rise and fall time.
6. Measured with 50 pF load
7. Measured at VOH =0.7 VDDD or VOL =0.2 VDDD. Measured from the 50% point of SCLK to the VOH
minimum of SDO.
13 of 14

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