DS1742-100 查看數據表（PDF） - Maxim Integrated

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DS1742-100

Y2KC Nonvolatile Timekeeping RAM

Maxim Integrated 

DS1742

RETRIEVING DATA FROM RAM OR CLOCK

The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is

high, and CE (chip enable) is low. The device architecture allows ripple-through access to any

of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA

after the last address input is stable, providing that the CE and OE access times and states are

satisfied. If CE or OE access times and states are not met, valid data will be available at the

latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data

input/output pins (DQ) is controlled by CE , and OE . If the outputs are activated before tAA, the

data lines are driven to an intermediate state until tAA. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then

go indeterminate until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a

write is referenced to the latter occurring transition of WE on CE . The addresses must be held

valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the

initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and

remain valid for tDH afterward. In a typical application, the OE signal will be high during a write

cycle. However, OE can be active provided that care is taken with the data bus to avoid bus

contention. If OE is low prior to WE transitioning low the data bus can become active with read

data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ

after WE goes active.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when VCC is greater than

VPF. However, when VCC is below the power fail point, VPF, (point at which write protection

occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls

below the battery switch point VSO (battery supply level), device power is switched from the VCC

pin to the backup battery. RTC operation and SRAM data are maintained from the battery until

VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or

read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to

the device is inhibited. If VPF is less than Vso, the device power is switched from VCC to the

backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is

switched from VCC to the backup supply (VBAT) when VCC drops below Vso. RTC operation and

SRAM data are maintained from the battery until VCC is returned to nominal levels.

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