DS1845 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1845

Dual NV Potentiometer and Memory

Dallas Semiconductor -> Maxim Integrated 

DS1845

6. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the

next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is

released.

7. After this period, the first clock pulse is generated.

8. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCL signal.

9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9(VCC) and (0.1)(VCC).

10. EEPROM write begins after a stop condition occurs.

11. Resistor inputs can not go beneath GND by more than 0.5V or above VCC by more that 0.5V.

12. The –3 dB cutoff frequency for the DS1845 is 1 MHz (10k/10k version).

13. Absolute linearity is used to measure expected wiper voltage as determined by wiper position. The

DS1845 is specified to provide an absolute linearity of ± 0.5 LSB (10k/10k version), ±1 LSB(10k/50k

version), and ± 1.5 LSB (10k/100k) version.

14. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper

positions. The DS1845 is specified to have a relative linearity of ± 0.25 dB.

15. When used as a rheostat or variable resister the temperature coefficient applies: 650 ppm/°C. When

used as a voltage divider or potentiometer, the effective temperature coefficient approaches

30 ppm/°C.

16. ICC specified with SDA pin open.

17. Maximum Icc is dependent on clock rates.

18. Valid for VCC = 5V only.

19. Valid at 25°C only.

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