DS1747-70 查看數據表（PDF） - Maxim Integrated

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DS1747-70

Y2K-Compliant, Nonvolatile Timekeeping RAMs

Maxim Integrated 

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs

AC TEST CONDITIONS

Output Load: 50 pF + 1TTL Gate

Input Pulse Levels: 0 to 3.0V

Timing Measurement Reference Levels:

Input: 1.5V

Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

NOTES:

1) Voltages are referenced to ground.

2) Typical values are at +25°C and nominal supplies.

3) Outputs are open.

4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.

5) Data-retention time is at +25°C.

6) Each DS1747 has a built-in switch that disconnects the lithium source until the user first applies VCC.

The expected tDR is defined for DIP modules and assembled PowerCap modules as accumulative time

in the absence of VCC starting from the time power is first applied by the user.

7) RTC encapsulated DIP (EDIP) modules can be successfully processed through conventional wave-

soldering techniques as long as temperatures as long as temperature exposure to the lithium energy

source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques

is acceptable, provided that ultra-sonic vibration is not used.

See the PowerCap package outline drawing for details regarding the PowerCap package.

8) tAH1, tDH1 are measured from WE going high.

9) tAH2, tDH2 are measured from CE going high.

10) tWC = 200ns.

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix

character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE

OUTLINE NO. LAND PATTERN NO.

32 EDIP

MDT32+4

21-0245

—

34 PWRCP

PC2+1

21-0246

—

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