SERIAL PORT TIMING – MODE 0
INSTRUCTION
0
1
2
3
4
5
6
7
DS2252T
8
ALE
CLOCK
36
DATA OUT
WRITE TO
SBUF REGISTER
INPUT DATA
CLEAR RI
35
37
0
1
2
39
38
VALID
VALID
VALID
3
4
VALID
VALID
5
6
7 SET TI
VALID
VALID
SET RI
NOTES:
1. All voltage referenced to ground.
2. SDI should be taken to a logic high when VCC=+5V, and to approximately 3V when VCC<3V.
3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitch-
er, but SDI is not guaranteed unless it is longer than tSPA.
4. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR,
tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC.
5. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns,
VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS.
6. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected;
RST = XTAL1 = VSS.
7. Pin capacitance is measured with a test frequency – 1 MHz, tA = 25°C.
8. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time
that power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The
user should check with the crystal vendor for a worst case specification on this time.
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