DS2282 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2282 Datasheet PDF : 22 Pages
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DS2282
USER REGISTER (14)
The DS2282 contains a 6–bit user port (pins UB1 to
UB6). An external controller can independently set or
clear these user bits via the User Bit Register (UBR).
The UBR is also used to select whether the DS2282 is to
operate in a T1.403 or a 54016 environment. If the
54016 bit is set to a one, then the DS2282 will operate in
a 54016 fashion and the 54016 register set will be se-
lected. If the 54016 bit is cleared (set to zero), then the
DS2282 will operate in a T1.403 fashion and the T1.403
register set will be selected. Operation in both modes
simultaneously is not allowed. If the user accesses the
opposite mode’s register set, a value of 00h is returned.
For example, 00h will be returned if the DS2282 is pro-
grammed for TR54016 mode and the user reads
address location 08h (CRCCR). The B8ZS bit should
be set to a one when the DS2282 is connected to T1
streams that include B8ZS code words. The default for
the UBR is 00 hex.
UBR: User Bit Register (14)
(MSB)
B8ZS 54016 UB6 UB5 UB4 UB3
(LSB)
UB2 UB1
B8ZS
54016
UB6
UB5
UB4
UB3
UB2
UB1
B8ZS Select. Logically OR’ed with the
B8ZS pin.
54016 Select. Set to a one in a 54016 en-
vironment.
User Bit 6. Sets or clears the UB6 pin.
User Bit 5. Sets or clears the UB5 pin.
User Bit 4. Sets or clears the UB4 pin.
User Bit 3. Sets or clears the UB3 pin.
User Bit 2. Sets or clears the UB2 pin.
User Bit 1. Sets or clears the UB1 pin.
54016 REGISTER SET SUMMARY Table 6
NAME
ADDR2,3 R/W CLEARABLE
CSR
20
R
No
ESFEER
21
R
No
CIT
22
R
No
CIESR
23
R
No
CIUASR
24
R
No
CIBESR
25
R
No
CISESR
26
R
No
CICSLFR
27
R
No
ESICR
28
R
No
DESCRIPTION
Current Status Register. An 8–bit register that indicates
unavailable signal state and PLB status.
ESF Error Event Register. A 16–bit register that accumu-
lates ESF error events.
Current Interval Timer. A 16–bit register that counts the
number of seconds in the current 15–minute interval.
Current Interval ES Register. A 16–bit register that indi-
cates the number of Errored Seconds in current 15–minute
interval.
Current Interval UAS Register. A 16–bit register that indi-
cates the number of Unavailable Seconds in current 15–min-
ute interval.
Current Interval BES Register. A 16–bit register that indi-
cates the number of Bursty Errored Seconds in current
15–minute interval.
Current Interval SES Register. A 16–bit register that indi-
cates the number of Severely Errored Seconds in current
15–minute interval.
Current Interval CSS & LOFC Register. A 16–bit register
that counts Controlled Slip Seconds and Loss of Frame in
current 15–minute interval. The 8–bit CSS count is in the
LSB and the 8–bit LOFC count is in the MSB.
ES Interval Count Registers. A set of 96 16–bit registers
that contain the Errored Second counts for the previous 96
individual 15–minute periods. Most recent interval is read
first.
022798 10/22
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