DS2465PT(2013) 查看數據表（PDF） - Maxim Integrated

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DS2465PT
(Rev.:2013)

DeepCover Secure Authenticator with SHA-256 Coprocessor and 1-Wire Master Function

Maxim Integrated 

ABRIDGED DATA SHEET

DS2465

DeepCover Secure Authenticator with

SHA-256 Coprocessor and 1-Wire Master Function

Pin Configuration

TOP VIEW

+

GND 1

IO 2

VCC 3

DS2465

6 SCL

5 SDA

4 SLPZ

Detailed Description

The DS2465 is a SHA-256 coprocessor with built-in

1-Wire master and two pages of user memory.

Refer to the full data sheet for this information.

TSOC

Pin Description

PIN NAME FUNCTION

1

GND Ground Reference

2

IO I/O Driver for 1-Wire Line

3

VCC Power-Supply Input

Active-Low Control Input. Activates the

low-power sleep mode and issues a

4 SLPZ device reset of the SHA-coprocessor and

the 1-Wire master (equivalent to the

1-Wire Master Reset command).

I2C Serial-Data Input/Output. Must be

5

SDA connected to VCC through a pullup

resistor.

6

SCL

I2C Serial-Clock Input. Must be connect-

ed to VCC through a pullup resistor.

The self-timed 1-Wire master function supports advanced

1-Wire waveform features including standard and over-

drive speeds, active pullup, and strong pullup for power

delivery. The active pullup affects rising edges on the

1-Wire side. The strong pullup function uses the same

pullup transistor as the active pullup, but with a differ-

ent control algorithm. Once supplied with command

and data, the input/output controller of the DS2465 per-

forms time-critical 1-Wire communication functions such

as reset/presence-detect cycle, read-byte, write-byte,

single-bit R/W, and triplet for ROM Search, without requir-

ing interaction with the host processor. The host obtains

feedback (completion of a 1-Wire function, presence

pulse, 1-Wire short, and search direction taken) through

the 1-Wire Master Status register and data through the

1-Wire Read Data register. All registers, the user memory

and a scratchpad are located in a linear address space

for direct access. The DS2465 communicates with a host

processor through its I2C bus interface in standard mode

or in fast mode. See Figure 1 for a block diagram.

Maxim Integrated

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