DS2465P(2013) 查看數據表（PDF） - Maxim Integrated

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DS2465P
(Rev.:2013)

DeepCover Secure Authenticator with SHA-256 Coprocessor and 1-Wire Master Function

Maxim Integrated 

ABRIDGED DATA SHEET

DS2465

DeepCover Secure Authenticator with

SHA-256 Coprocessor and 1-Wire Master Function

1-Wire Master Configuration Register (67h)

The DS2465 supports four 1-Wire features that are enabled or selected through the 1-Wire Master Configuration regis-

ter (Table 3). These features are: Active Pullup (APU), 1-Wire Power-Down (PDN), Strong Pullup (SPU), 1-Wire Speed

(1WS). APU, SPU and 1WS can be selected in any combination. While APU and 1WS maintain their state, SPU returns

to its inactive state as soon as the strong pullup has ended.

After a device reset (power-up cycle, a low pulse at SLPZ, or initiated by the 1-Wire Master Reset command), the 1-Wire

Master Configuration register reads 00h. When writing to the register, the new data is accepted only if the upper nibble

(bits 7 to 4) is the one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.

Table 3. 1-Wire Master Configuration Bit Assignment

BIT 7

1WS

BIT 6

SPU

BIT 5

PDN

BIT 4

APU

BIT 3

1WS

BIT 2

SPU

BIT 1

PDN

BIT 0

APU

Bit 3: 1-Wire Speed (1WS). The 1WS bit determines the timing of any 1-Wire communication generated by the DS2465.

Most 1-Wire slave devices support standard speed (1WS = 0). Many 1-Wire devices can also communicate at a higher

data rate, called overdrive speed. Some 1-Wire devices, including the DeepCover SHA-256 family of slave devices,

only support overdrive and 1WS should always be programmed high for these devices. To change from standard to

overdrive speed, a 1-Wire device needs to receive an Overdrive-Skip ROM or Overdrive-Match ROM command, as

explained in the 1-Wire device data sheets. The change in speed occurs immediately after the 1-Wire device has

received the speed-changing command code. The DS2465 must take part in this speed change to stay synchronized.

This is accomplished by writing to the 1-Wire Master Configuration register with the 1WS bit as 1 immediately after the

1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the 1-Wire Master Configuration register

with the 1WS bit as 0, followed by a 1-Wire Reset command, changes the DS2465 and any 1-Wire devices on the active

1-Wire line back to standard speed.

Bit 2: Strong Pullup (SPU). The SPU bit is used to activate the strong pullup function prior to a 1-Wire Write Byte, 1-Wire

Read Byte, or 1-Wire Single Bit command. Strong pullup is commonly used with 1-Wire EEPROM devices when copy-

ing scratchpad data to the main memory or when performing a SHA computation. The respective device data sheets

specify the location in the communications protocol after which the strong pullup should be applied. The SPU bit must

be set immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra

power. The strong pullup uses the same internal pullup transistor as the active pullup feature. See the RAPU parameter

in the Electrical Characteristics to determine whether the voltage drop is low enough to maintain the required 1-Wire

voltage at a given load current and supply voltage.

If SPU is 1, the DS2465 treats the rising edge of the time slot in which the strong pullup starts as if the active pullup was

activated. However, in contrast to the active pullup, the strong pullup, i.e., the internal pullup transistor, remains con-

ducting, as shown in Figure 3, until one of four events occurs: the DS2465 receives a command that generates 1-Wire

communication (the typical case); the SPU bit in the 1-Wire Master Configuration register is written to 0; the PDN bit

in the 1-Wire Master Configuration register is written to 1; or the DS2465 receives the 1-Wire Master Reset command.

When the strong pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup feature does not change

the state of the APU bit in the 1-Wire Master Configuration register.

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