DS3234(2006) 查看數據表（PDF） - Maxim Integrated

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DS3234
(Rev.:2006)

Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM

Maxim Integrated 

Extremely Accurate SPI Bus RTC with

Integrated Crystal and SRAM

Temperature Control (13h/93h)

NAME:

POR*:

BIT 7

0

0

BIT 6

0

0

BIT 5

0

0

BIT 4

0

0

BIT 3

0

0

*POR is defined as the first application of power to the device, either VBAT or VCC.

BIT 2

0

0

BIT 1

0

0

BIT 0

BB_TD

0

SRAM Address (18h/98h)

NAME:

BIT 7

A7

BIT 6

A6

BIT 5

A5

BIT 4

A4

BIT 3

A2

BIT 2

A1

BIT 1

A1

BIT 0

A0

SRAM Data (19h/99h)

NAME:

BIT 7

D7

BIT 6

D6

BIT 5

D5

BIT 4

D4

Note: These registers do not default to any specific value.

Temperature Control

Register (13h/93h)

Bit 0: Battery-Backed Temperature Conversion

Disable (BB_TD). The battery-backed tempconv dis-

able bit prevents automatic temperature conversions

when the device is powered by the VBAT supply. This

reduces the battery current at the expense of frequen-

cy accuracy.

SRAM Address Register

(18h/98h)

The SRAM address register provides the 8-bit address

of the 256-byte memory array. The desired memory

address should be written to this register before the

data register is accessed. The contents of this register

are incremented automatically if the data register is

accessed more than once during a single transfer.

When the contents of the address register reach 0FFh,

the next access causes the register to roll over to 00h.

SRAM Data Register (19h/99h)

The SRAM data register provides the data to be written

to or the data read from the 256-byte memory array.

During a read cycle, the data in this register is that

found in the memory location in the SRAM address reg-

ister (18h/98h). During a write cycle, the data in this reg-

ister is placed in the memory location in the SRAM

address register (18h/98h). When the SRAM data regis-

ter is read or written, the internal register pointer

remains at 19h/99h and the SRAM address register

increments after each byte that is read or written, allow-

ing multibyte transfers.

BIT 3

D2

BIT 2

D1

BIT 1

D1

BIT 0

D0

SPI Serial Data Bus

The DS3234 provides a 4-wire SPI serial data bus to com-

municate in systems with an SPI host controller. The

DS3234 supports both single byte and multiple byte data

transfers for maximum flexibility. The DIN and DOUT pins

are the serial data input and output pins, respectively.

The CS input is used to initiate and terminate a data

transfer. The SCLK pin is used to synchronize data move-

ment between the master (microcontroller) and the slave

devices (see Table 3). The shift clock (SCLK), which is

generated by the microcontroller, is active only during

address and data transfer to any device on the SPI bus.

Input data (DIN) is latched on the internal strobe edge

and output data (DOUT) is shifted out on the shift edge

(Figure 2). There is one clock for each bit transferred.

Address and data bits are transferred in groups of eight.

CS

DATA LATCH (WRITE/INTERNAL STROBE)

SHIFT DATA OUT (READ)

SCLK WHEN CPOL = 0

DATA LATCH (WRITE/INTERNAL STROBE)

SHIFT DATA OUT (READ)

SCLK WHEN CPOL = 1

NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.

NOTE 2: CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER.

NOTE 3: DOUT REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE

SHIFTED OUT DURING A READ.

Figure 2. Serial Clock as a Function of Microcontroller Clock-

Polarity Bit

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