Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Pushbutton Reset Timing
RST
PBDB
tRST
VCC
VPF(MAX)
VPF(MIN)
RST
VPF
tVCCF
Power-Switch Timing
VPF
tVCCR
tREC
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: Measured at VIH = 0.8 x VCC or VIL = 0.2 x VCC, 10ns rise/fall time, DOUT = no load.
Note 4: Current is the averaged input current, which includes the temperature conversion current. CRATE1 = CRATE0 = 0.
Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.
Note 6: Measured at VOH = 0.8 x VCC or VOL = 0.2 x VCC. Measured from the 50% point of SCLK to the VOH minimum of DOUT.
Note 7: With 50pF load.
Note 8: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ VBAT(MAX).
Note 9: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately
goes high.
Note 10: Guaranteed by design and not production tested.
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