DS7505(2015) 查看數據表（PDF） - Maxim Integrated
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DS7505 Datasheet PDF : 14 Pages
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DS7505
Digital Thermometer and Thermostat
Table 3. Resolution Configuration
R1
R0
THERMOMETER MAX CONVERSION
RESOLUTION (BITS)
TIME (ms)
0
0
9
25
0
1
10
50
1
0
11
100
1
1
12
200
Table 4. Fault Tolerance Configuration
F1 F0
0
0
0
1
1
0
1
1
CONSECUTIVE OUT-OF-LIMITS
CONVERSIONS TO TRIGGER O.S.
1
2
4
6
Register Pointer
The four DS7505 registers each have a unique 2-bit
pointer designation, which is defined in Table 5. When
reading from or writing to the DS7505, the user must
“point” the DS7505 to the register that is to be accessed.
When reading from the DS7505, once the pointer is set,
it remains pointed at the same register until it is changed.
For example, if the user desires to perform consecutive
reads from the temperature register, then the pointer only
has to be set to the temperature register one time, after
which all reads are automatically from the temperature
register until the pointer value is changed. When writing
to the DS7505, the pointer value must be refreshed each
time a write is performed, even if the same register is
being written to twice in a row.
At power-up, the pointer defaults to the temperature
register location. The temperature register can be read
immediately without resetting the pointer.
Changes to the pointer setting are accomplished as
described in the 2-Wire Serial Data Bus section.
Table 5. Pointer Definition
REGISTER
P1
P0
Temperature
0
0
Configuration
0
1
THYST
TOS
1
0
1
1
2-Wire Serial Data Bus
The DS7505 communicates over a standard bidirectional
2-wire serial data bus that consists of a serial clock (SCL)
signal and serial data (SDA) signal. The DS7505 inter-
faces to the bus through the SCL input pin and open-drain
SDA I/O pin. All communication is MSB first.
The following terminology is used to describe 2-wire
communication:
Master Device: Microprocessor/microcontroller that
controls the slave devices on the bus. The master
device generates the SCL signal and START and STOP
conditions.
Slave: All devices on the bus other than the master. The
DS7505 always functions as a slave.
Bus Idle or Not Busy: Both SDA and SCL remain high.
SDA is held high by a pullup resistor when the bus is idle,
and SCL must either be forced high by the master (if the
SCL output is push-pull) or pulled high by a pullup resistor
(if the SCL output is open drain).
Transmitter: A device (master or slave) that is sending
data on the bus.
Receiver: A device (master or slave) that is receiving
data from the bus.
START Condition: Signal generated by the master to
indicate the beginning of a data transfer on the bus. The
master generates a START condition by pulling SDA from
high to low while SCL is high (see Figure 6). A “repeated”
START is sometimes used at the end of a data transfer
(instead of a STOP) to indicate that the master performs
another operation.
STOP Condition: Signal generated by the master to
indicate the end of a data transfer on the bus. The master
generates a STOP condition by transitioning SDA from low
to high while SCL is high (see Figure 6). After the STOP is
issued, the master releases the bus to its idle state.
Acknowledge (ACK): When a device (either master
or slave) is acting as a receiver, it must generate an
acknowledge (ACK) on the SDA line after receiving every
byte of data. The receiving device performs an ACK by
pulling the SDA line low for an entire SCL period (see
Figure 6). During the ACK clock cycle, the transmitting
device must release SDA. A variation on the ACK signal is
the “not acknowledge” (NACK). When the master device
is acting as a receiver, it uses a NACK instead of an ACK
after the last data byte to indicate that it is finished receiv-
ing data. The master indicates a NACK by leaving the
SDA line high during the ACK clock cycle.
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