DSP56011 查看數據表（PDF） - Motorola => Freescale

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DSP56011

24-BIT DVD DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6 Phase Lock Loop (PLL) Characteristics

PRELIMINARY Characteristics

Expression

Min

Max

Unit

VCO frequency when PLL enabled

PLL external capacitor (PCAP pin to

VCCP)

MF × EF

MF × CPCAP

@ MF ≤ 4

@ MF > 4

10

f

MHz

MF × 340 MF × 480 pF

MF × 380 MF × 970 pF

Note:

Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1.

The recommended value for Cpcap is 400 pF for MF ≤ 4 and 540 pF for MF > 4.

The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

All Frequencies

Min

Max

10 Minimum RESET assertion width:

• PLL disabled

• PLL enabled1

14 Mode select setup time

25 × TC

—

2500 × ETC

—

21

—

15 Mode select hold time

0

—

16 Minimum edge-triggered interrupt request assertion

13

—

width

16a Minimum edge-triggered interrupt request

deassertation width

13

—

18 Delay from IRQA, IRQB, NMI assertion to GPIO valid

caused by first interrupt instruction execution

• GPIO0–GPIO7

12 × TC + TH

—

Unit

ns

ns

ns

ns

ns

ns

ns

• PB0–PB14

11 × TC + TH

—

ns

Preliminary Information

2-6

DSP56011 Technical Data Sheet, Rev. 1

MOTOROLA

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