K4S161622E-TC80 查看數據表（PDF） - Samsung

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K4S161622E-TC80

1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL

Samsung 

K4S161622E

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter

Symbol

Test Condition

CAS

Latency -55

Version

-60 -70 -80

-10

Unit

Note

Operating Current

(One Bank Active)

Burst Length =1

ICC1

tRC≥tRC(min)

Io = 0 mA

3 120 115 105 95 85

mA 2

2

- - 95 95 80

Precharge Standby Current

in power-down mode

ICC2P

ICC2PS

CKE≤VIL(max), tCC = 15ns

CKE & CLK≤VIL(max), tCC = ∞

2

mA

2

Precharge Standby Current

in non power-down mode

ICC2N

ICC2NS

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

15

5

mA

Active Standby Current

in power-down mode

ICC3P

ICC3PS

CKE≤VIL(max), tCC = 15ns

CKE & CLK≤VIL(max), tCC = ∞

3

mA

3

Active Standby Current

ICC3N

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

25

mA

in non power-down mode

(One Bank Active)

ICC3NS

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

15

mA

Operating Current

(Burst Mode)

Io = 0 mA

3 155 150 140 130 115

ICC4

Page Burst 2Banks Activated

mA 2

tCCD = 2CLKs

2

- - 115 115 100

Refresh Current

ICC5

Self Refresh Current

ICC6

tRC≥tRC(min)

CKE≤0.2V

3 105 100 90 90 80

mA 3

2

- - 90 90 80

1

mA 4

Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4. K4S161622E-TC**

Rev 1.1 Jan '03

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