E602204_HD64413A 查看數據表（PDF） - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

• Clock generator (CPG0, CPG1)

The Q2SD operating clock is generated in the CPG0, and it is provided to each unit

excluding the display unit. The display dot clock is generated in the CPG1 and it is provided

to the display unit.

• Rendering unit

Performs fetching and interpretation of the display list in the UGM.

• Rendering buffer unit

Buffers data and addresses between the rendering unit and the UGM to improve the

efficiency to the UGM access in the rendering unit.

• Display unit

Generates the CRT control signals and outputs analog RGB signals.

• Display buffer unit

Composes the foreground, background, video and cursor screens. Accesses data to be

displayed in synchronization with the display timing. By the color palette (6 bits per color),

converts 8-bits/pixel data to display data of 256 colors out of 262,144 to the RGB data, based

on the color conversion table, and when the video screen data is the YCbCr data, it is

converted to the RGB data.

• Video-in unit

Fetches 4:2:2 YCbCr data and stores it in the UGM in YCbCr or RGB format. The image

data can also be stored with reduction.

Rev. 2.0, 09/02, page 11 of 366

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