EDI2GG464128V 查看數據表（PDF） - White Electronic Designs Corporation
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EDI2GG464128V Datasheet PDF : 8 Pages
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EDI2GG464128V
4x128Kx64 Synchronous SRAM CARD EDGE DIMM, 3.3V
FEATURES
s 4x128Kx64 Synchronous
s Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns
s Flow-Through Architecture
s Clock Controlled Registered Bank Enables (E1\, E2\, E3, E4\)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW\)
s Aysnchronous Output Enable (G\)
s Internally self-timed Write
s Gold Lead Finish
s 3.3V ±10%, -5% Operation
s Common Data I/O
s High Capacitance (30pF) drive, at rated Access Speed
s Single total array Clock
s Multiple Vcc and Vss
The EDI2GG464128VxxD is a Synchronous SRAM, 60 position
Card Edge DIMM (120 contacts) Module, organized as 4x128Kx64.
The Module contains eight (8) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm TQFP
placed on a Multilayer FR4 Substrate. The module architecture is
defined as a Synchronous Only, Flow-Through, Early Write De-
vice. This module provides High Performance, Ultra Fast access
times at a cost per bit benefit over BiCMOS Asynchronous SRAM
based devices. As well as improved cost per bit, the use of
Synchronous or Synchronous Burst devices or modules can ease
the memory subsystem design by reducing or easing the memory
controller requirement.
Synchronous operations are in relation to an externally supplied
clock, Registered Address, Registered Global Write, Registered
Enables as well as an Asynchronous Output enable. All read and
write operations to this module are performed on Quad Words (64
bit operations).
Write cycles are internally self timed and are initiated by a rising
clock edge. This feature relieves the designer the task of devel-
oping external write pulse width circuitry.
November 1998 Rev. 0
ECO# 10855
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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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