EL5128 查看數據表（PDF） - Intersil
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EL5128 Datasheet PDF : 12 Pages
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EL5128
where:
• TJMAX = Maximum junction temperature
• TAMAX= Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
PDMAX = Σi × [VS × ISMAX + (VS + - VOUTi ) × ILOADi]
when sourcing, and:
PDMAX = Σi × [VS × ISMAX + (VOUT i - VS- ) × ILOADi]
when sinking.
where:
• VS = Total supply voltage
• ISMAX = Maximum supply current per amplifier
• VOUTi = Maximum output voltage of the application
• ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figures 27
and 28 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves in Figures 27
and 28.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
0.5
486mW
0.4
0.3
0.2
θJJAA=2M0S6°O°CCP//W1W0
0.1
0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.8 870mW
0.7
0.6
0.5
0.4
θJA =1M15S°OCP/W10
0.3
0.2
0.1
0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5128 can provide gain at high frequency. As with any
high-frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1µF ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the amplifier.
One 4.7µF capacitor may be used for multiple devices. This
same capacitor combination should be placed at each
supply pin to ground if split supplies are to be used.
11
FN7000.3
May 4, 2007
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