EL7520AILZ-T7 查看數據表（PDF） - Intersil
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EL7520AILZ-T7 Datasheet PDF : 18 Pages
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EL7520, EL7520A
under the low dropout condition (forced beta of 10). Typical
VLOGIC voltage supported by EL7520, EL7520A range from
+1.3V to VDD-0.2V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 25% below the 1.2V reference.
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of
VON, VOFF, and VLOGIC are determined by the following
equations:
VON
=
VREF
×
1
+
RR-----11---21-
VOFF
=
VR
E
F
N
+
R-----2---2-
R21
×
(
VREF
N
–
VR
EF)
VLOGIC
=
VR
E
F
×
1
+
R-R----44---21-
Where VREF = 1.2V, VREFN = 0.2V.
Charge Pump
To generate an output voltage higher than VBOOST, single or
multi stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
NPOSITIVE ≥ V-----O----VU----IT--N---+--P---VU----C-T---E-–----–-2----V-×---I-V-N----FP----U----T--
where VCE is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor. VF is the forward-voltage of the charge pump
rectifier diode.
The number of negative charge pump stages is given by:
NNEGATIVE ≥ --V-V---O-I--N--U--P--T--U-P---T-U----–-T---2---+--×---V--V--C--F--E--
To achieve high efficiency and low material cost, the lowest
number of charge pump stages, which can meet the above
requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
CO
U
T
≥
---------------------I--O----U-----T----------------------
2 × VRIPPLE × fOSC
Where fSOC is the switching frequency.
Start-Up Sequence
Figures 30 and 31 show detailed start-up sequence
waveforms, EL7520 and EL7520A, respectively. For a
successful power-up, there should be six peaks at VCDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (VDD) exceeds 2.5V, an internal current source
starts to charge CDLY to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
CDLY ramp will be delayed until EN goes high.
The first four ramps on CDLY (two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on CDLY or VREF. If a fault is
detected, the outputs and the input protection will turn off and
the chip will power down. For EL7520A, VREF will stay on.
If no fault is found, CCDLY continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
VREF and over temperature. At the peak of the second ramp,
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
VBOOST before VBOOST is enabled internally. Its rate of turn
on is controlled by Co. When a fault is detected, Q1 will turn
off and disconnect the inductor from VIN.
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~VIN. Initially the boost is not
enabled so VBOOST rises to VIN-VDIODE through the output
diode. Hence, there is a step at VBOOST during this part of the
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at AVDD.
For EL7520, VBOOST and VLOGIC soft-start at the beginning
of the third ramp. The soft-start ramp depends on the value
of the CDLY capacitor. For CDLY of 220nF, the soft-start time
is ~2ms. EL7520A is the same as EL7520 except that VREF
and VLOGIC turn on once input voltage exceeds 2.5V.
VOFF turns on at the start of the fourth peak. At the fifth
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed VBOOST output.
VON is enabled at the beginning of the sixth ramp. AVDD,
PG, VOFF, DELB and VON are checked at end of this ramp.
14
FN7318.0
July 12, 2005
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