EM636327TQ-55 查看數據表（PDF） - Etron Technology

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EM636327TQ-55

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Etron Technology 

EtronTech

DSF

DQ

BankActivate CK

command

MR7

DQM0

MR6

MR5

MR4

MR3

MR2

MR1

MR0

EM636327

DQ7

DQ6

DRAM

CELL

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

0 = Masked

1 = Not Masked

Note: Only the lower byte is shown. The operation is identical for other bytes.

Write Per Bit (I/O Mask) Block Diagram

A write burst without the auto precharge function may be interrupted by a subsequent

Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst

length. An interrupt coming from Write/Block Write command can occur on any clock cycle

following the previous Write command (refer to the following figure).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

DQ's

NOP

WRITE A WRITE B

1 Clk Interval

DIN A0

DIN B0

NOP

DIN B1

NOP

NOP

DIN B2

DIN B3

NOP

NOP

NOP

Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)

The Read command that interrupts a write burst without auto precharge function should be

issued one cycle after the clock edge in which the last data-in element is registered. In order to

avoid data contention, input data must be removed from the DQs at least one clock cycle before the

Preliminary

10

December 1998

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