EM636327TQ-55 查看數據表（PDF） - Etron Technology

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EM636327TQ-55

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Etron Technology 

EtronTech

EM636327

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 2 shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command

State CKEn-1 CKEn DQM(7) BS A9 A0-8 CS# RAS# CAS# WE# DSF

BankActivate & Masked Write Disable

Idle(3)

H

X

X VV V L L

H HL

BankActivate & Masked Write Enable

Idle(3)

H

X

X VV V L L

H HH

BankPrecharge

Any

H X X VL X L L H L L

PrechargeAll

Any

H X X XH X L L H L L

W rite

Active(3) H

X

X VL V L H

L LL

Block Write Command

Active(3) H

X

X VL V L H

L LH

Write and AutoPrecharge

Active(3) H

X

X VH V L H

L LL

Block Write and AutoPrecharge

Active(3) H

X

X VH V L H

L LH

Read

Active(3) H

X

X VL V L H

L HL

Read and Autoprecharge

Active(3) H

X

X VH V L H

L HL

Mode Register Set

Idle

H X X VL V L L L L L

Special Mode Register Set

Idle(5)

H

X

X XX V L L

L LH

No-Operation

Any

H X X XX X L H H H X

Burst Stop

Active(4) H

X

X XX X L H H L L

Device Deselect

Any

H X X XX X H X X X X

AutoRefresh

Idle

H H X XX X L L L H L

SelfRefresh Entry

Idle

H L X XX X L L L H L

SelfRefresh Exit

Idle

L H X XX X H X X X X

(SelfRefresh)

L H H HX

Clock Suspend Mode Entry

Active H L X X X X X X X X X

Power Down Mode Entry

Any(6)

H

L

X XX X H X X X X

L H H HL

Clock Suspend Mode Exit

Active L H X X X X X X X X X

Power Down Mode Exit

Any

L H X XX X H X X X X

(PowerDown)

L H H HL

Data Write/Output Enable

Active H X L X X X X X X X X

Data Mask/Output Disable

Active H X H X X X X X X X X

Note:

1. V=Valid X=Don't Care L=Low level H=High level

2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BS signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. The Special Mode Register Set is also available in Row Active State.

6. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

7. DQM0-3

Preliminary

5

December 1998

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