EM636327TQ-55 查看數據表（PDF） - Etron Technology

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EM636327TQ-55

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Etron Technology 

EtronTech

T0

T1

T2

T3

CLK

DQM

T4

T5

EM636327

T6

T7

T8

C OM M A ND

NOP

READ A

NOP

NOP

NOP

NOP

WRITE B

NOP

DQ's

: "H" or "L"

DOUT A0

Must be Hi-Z before

the Write Command

DINB0

DINB1

Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 3)

NOP

DINB2

CLK

DQM

T0

T1

T2

T3

T4

T5

T6

T7

T8

1 Clk Interval

C OM M A ND

NOP

NOP

BANKA

ACTIVATE

NOP

READ A WRITE A

NOP

NOP

CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

: "H" or "L"

Must be Hi-Z before

the Write Command

DIN A0

DIN A0

DIN A1

DIN A1

DIN A2

DIN A2

Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 1, 2)

NOP

DIN A3

DIN A3

CLK

DQM

T0

T1

T2

T3

T4

T5

T6

T7

T8

C OM M A ND

NOP

NOP

READ A

NOP

NOP

WRITE B

NOP

NOP

NOP

CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

: "H" or "L"

DOUT A0

DIN B0

Must be Hi-Z before

the Write Command

DIN B0

DIN B1

DIN B1

DIN B2

DIN B2

Read to Write Interval (Burst Length ¡Ù 4, CAS# Latency = 1, 2)

DIN B3

DIN B3

A read burst without the auto precharge function may be interrupted by a BankPrecharge/

PrechargeAll command to the same bank. The following figure shows the optimum time that

BankPrecharge/ PrechargeAll command is issued in different CAS# latency.

Preliminary

8

December 1998

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