EM78808ICE 查看數據表（PDF） - ELAN Microelectronics

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EM78808ICE

8-BIT MICRO-CONTROLLER

ELAN Microelectronics 

EM78808

8-bit Micro-controller

Bit 6 (PLLEN) : PLL enable control bit

It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency,

main clock); otherwise, it will run at green mode (low frequency, 32768 Hz).

0/1 disable/enable

3.5826MHz to analog circuit

Sub-clock

32.768kHz

PLL

ENPLL

÷ 4 =>895.658kHz

÷ 2 =>1.7913MHz

× 1 =>3.5826MHz

× 3 =>10.7479MHz

CLK1 ~ CLK0

1

switch

0

System clock

Fig.10 The relation between 32.768kHz and PLL

Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!

The status after wake-up and the wake-up sources list as the table below.

Wakeup signal

SLEEP mode

RA(7,6)=(0,0)

+ SLEP

GREEN mode

RA(7,6)=(x,0)

no SLEP

NORMAL mode

RA(7,6)=(x,1)

no SLEP

TCC time out

IOCF bit 0=1

And "ENI"

No function

Interrupt

Interrupt

(jump to address 8 (jump to address

at page0)

8 at page0)

COUNTER1 time out

IOCF bit 1=1

And "ENI"

COUNTER2 time out

IOCF bit 2=1

And "ENI"

No function

No function

Interrupt

Interrupt

(jump to address 8 (jump to address

at page0)

8 at page0)

Interrupt

Interrupt

(jump to address 8 (jump to address

at page0)

8 at page0)

WDT time out

RESET and RESET and Jump RESET and

Jump to address to address 0

Jump to address

0

0

PORT7

IOCF bit3 or bit4 or

bit5 = 1

And "ENI"

RESET and Interrupt

Interrupt

Jump to address (jump to address 8 (jump to address

0

at page0)

8 at page0)

DED interrupt

IOCE page2 bit 6 = 1

And RE page1 bit6

logic level variation

(switch by EDGE bit)

And “ENI”

Stack overflow

IOC5 page2 bit7=1

&bit 6: 0 1

And “ENI”

No function

No function

Interrupt

Interrupt

(jump to address 8 (jump to address

at page0)

8 at page0)

Interrupt

Interrupt

(jump to address 8 (jump to address

at page0)

8 at page0)

<Note> Stack overflow interrupt function is exist in ROM less and OTP chip only.

<Note> PORT70 ~ PORT73 's wakeup function is controlled by IOCF bit3 and ENI instruction. They are

falling edge trigger.

______________________________________________________________________________________________________________________________________________________

* This specification is subject to change without notice.

8/1/2004 (V3.1)

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