EM78P142
8-Bit Microprocessor with OTP ROM
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit
0 = Disable Low Voltage Detect wake-up
1 = Enable Low Voltage Detect wake-up
When the Low Voltage Detect is used to enter an interrupt vector or to
wake-up the IC from sleep/idle with Low Voltage Detect running, the
LVDWE bit must be set to “Enable“.
6.1.15 RF (Interrupt Status 2 Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF
Bit 2
“0”
Note: 1. “1” means there is interrupt request, “0”
2. RF can be cleared by instruction but cannot be set.
3. IOCF0 is the interrupt mask register.
4. Reading RF will result to “logic AND” of the RF and IOCF0
Bit 1
ICIF
Bit 0
TCIF
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCB overflows. Reset by
software.
Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCA overflows. Reset by
software.
Bit 2:
This bit must be set to “0” all the time.
Bit 1 (ICIF):
Port 5 input status change interrupt flag. Set when Port 5 input
changes. Reset by software.
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
6.1.16 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
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