EM78P153E 查看數據表（PDF） - ELAN Microelectronics

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EM78P153E

8-bit microprocessor designed and developed with low-power and high-speed CMOS technology

ELAN Microelectronics 

EM78P153E

OTP ROM

Address

Name

Reset Type

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/RESET and WDT

1

1

1

1

1

1

1

1

Wake-Up from Pin Change P

P

P

P

P

P

PP

Bit Name

OD7 OD6 OD5 OD4 X OD2 OD1 OD0

0x0C

IOCC

Power-On

/RESET and WDT

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Wake-Up from Pin Change P

P

P

P

P

P

PP

Bit Name

/PH7 /PH6 /PH5 /PH4 X /PH2 /PH1 /PH0

0x0D

IOCD

Power-On

/RESET and WDT

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Wake-Up from Pin Change P

P

P

P

P

P

PP

Bit Name

WDTE EIS X

X

X

X

XX

0x0E

IOCE

Power-On

/RESET and WDT

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

Wake-Up from Pin Change P

P

1

1

1

1

1

1

Bit Name

X

X

X

X

X EXIE ICIE TCIE

0x0F

IOCF

Power-On

/RESET and WDT

1

1

1

1

1

0

0

0

1

1

1

1

1

0

0

0

Wake-Up from Pin Change 1

1

1

1

1

P

PP

Bit Name

-

-

-

-

-

-

-

-

0x10~0x2F R10~R2F

Power-On

/RESET and WDT

U

U

U

U

U

U

UU

P

P

P

P

P

P

PP

Wake-Up from Pin Change P

P

P

P

P

P

PP

X: not used. U: unknown or don’t care. P: previous value before reset. t: check Table 4

2. /RESET Configure

Refer to Fig. 10 When the RESET bit in the OPTION word is programmed to 0, the external /RESET

is enabled. When programmed to 1, the internal /RESET is enabled, tied to the internal Vdd and the

pin is defined as P63.

3. The status of RST, T, and P of STATUS register

A RESET condition is initiated by the following events:

1. A power-on condition,

2. A high-low-high pulse on /RESET pin, and

3. Watchdog timer time-out.

The values of RST, T, and P, listed in Table 4 are used to check how the processor wakes up. Table

5 shows the events which may affect the status of RST, T, and P.

This specification is subject to change without prior notice.

20

2002/03/01

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