FIN3385MTDX 查看數據表（PDF） - Fairchild Semiconductor
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FIN3385MTDX
Fairchild Semiconductor
FIN3385MTDX Datasheet PDF : 21 Pages
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Receiver AC Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
tRSKM
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
RxIn Skew Margin(19)
0.7
1.1
1.4
2.9
3.3
3.6
5.1
5.5
5.8
Figure 21, f=66MHz
7.3
7.7
8.0
ns
9.5
9.9
10.2
11.7 12.1 12.4
13.9 14.3 14.6
f=40MHz, Figure 21 490
ps
f=66MHz, Figure 21 400
tRPLLS Receiver Phase Lock Loop Set Time
Figure 15
10.0 ms
Notes:
14. The power supply current for the receiver can vary with the number of I/O channels.
15. Total channel latency from serializer to deserializer is (t + tTCCD) where t is a clock period.
16. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum/maximum bit position.
17. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with
rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold
time tRHRC, the clock reference point is the time when falling edge passes through +0.8V.
18. Total channel latency from serializer to deserializer is (t + tCCD) (2•t + tRCCD) where t is the clock period.
19. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum / maximum bit position.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
12
www.fairchildsemi.com
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