Q0765R_08 查看數據表（PDF） - Fairchild Semiconductor

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Q0765R_08

Green-Mode Fairchild Power Switch (FPS™) for Quasi-Resonant Operation - Low EMI and High Efficiency

Fairchild Semiconductor 

uses a sync signal instead of directly monitoring the

output voltage. If the sync signal exceeds 8V, an OVP is

triggered, shutting down the SMPS. To avoid undesired

triggering of OVP during normal operation, there are 2

points to be considered which is depicted in Figure 32.

One is the making the peak voltage of the sync signal

should be designed below 6V and the other is that be

sure to make the spike of sync pin as los as possible not

to get longer than tOVP by decreasing the leakage

inductance shown at VCC winding coil.

VVcc_coil &VCC

FSQ0765R Rev.00

Absolue max VCC (20V)

VCC

VVcc_coil

6. Burst Operation: To minimize power dissipation in

standby mode, the FPS enters burst-mode operation. As

the load decreases, the feedback voltage decreases. As

shown in Figure 33, the device automatically enters

burst-mode when the feedback voltage drops below

VBURL (350mV). At this point, switching stops and the

output voltages start to drop at a rate dependent on

standby current load. This causes the feedback voltage

to rise. Once it passes VBURH (550mV), switching

resumes. The feedback voltage then falls and the

process repeats. Burst-mode operation alternately

enables and disables switching of the power SenseFET,

thereby reducing switching loss in standby mode.

VO

VOset

Vsync

Improper OVP triggering

VOVP (8V)

tOVP

VSH2 (4.8V)

VDC

Npri

NVcc

tOVP

VFB

0.55V

0.35V

IDS

VCLAMP

VDS

Figure 32. OVP Triggering

4.5 Thermal Shutdown with Hysteresis (TSD): The

SenseFET and the control IC are built in one package.

This makes it easy for the control IC to detect the

abnormally high temperature of the SenseFET. If the

temperature exceeds approximately 140°C, the thermal

shutdown triggers IC shutdown. The IC recovers its

operation when the junction temperature decreases

60°C from TSD temperature and VCC reaches start-up

voltage (Vstart).

5. Soft-Start: The FPS has an internal soft-start circuit

that increases PWM comparator inverting input voltage

with the SenseFET current slowly after it starts up. The

typical soft-start time is 17.5ms. The pulse width to the

power switching device is progressively increased to

establish the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention of

smoothly establishing the required output voltage. This

mode helps prevent transformer saturation and reduces

stress on the secondary diode during start-up.

FSQ0765R Rev.00

Switching

Switching

t1

disabled

t2 t3 disabled

t4

time

Figure 33. Waveforms of Burst Operation

7. Switching Frequency Limit: To minimize switching

loss and Electromagnetic Interference (EMI), the

MOSFET turns on when the drain voltage reaches its

minimum value in quasi-resonant operation. However,

this causes switching frequency to increases at light load

conditions. As the load decreases or input voltage

increases, the peak drain current diminishes and the

switching frequency increases. This results in severe

switching losses at light-load condition, as well as

intermittent switching and audible noise. These problems

create limitations for the quasi-resonant converter

topology in a wide range of applications.

To overcome these problems, FSQ-series employs a

frequency-limit function, as shown in Figures 34 and 35.

Once the SenseFET is turned on, the next turn-on is

prohibited during the blanking time (tB). After the

blanking time, the controller finds the valley within the

detection time window (tW) and turns on the MOSFET, as

shown in Figures 34 and Figure 35 (Cases A, B, and C).

© 2008 Fairchild Semiconductor Corporation

FSQ0565R, FSQ0765R Rev. 1.0.1

15

www.fairchildsemi.com

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