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HD404338 查看數據表(PDF) - Renesas Electronics

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HD404338 Datasheet PDF : 80 Pages
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HD404339 Series
Notes on Usage
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
Do not write to the A/D start flag during A/D conversion
Data in the A/D data register during A/D conversion is undefined
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these
modes, all current flowing through the converter’s resistance ladder is cut off.
If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain
pulled up.
A/D mode register 1 (AMR1: $019)
Bit
Initial value
Read/Write
Bit name
3
0
W
AMR13
2
1
0
0
W
W
AMR12 AMR11
0
0
W
AMR10
AMR12
0
1
AMR13
0
1
R32/AN2 Mode Selection
R32
AN2
R33/AN3 Mode Selection
R33
AN3
AMR10
0
1
AMR11
0
1
R30/AN0 Mode Selection
R30
AN0
R31/AN1 Mode Selection
R31
AN1
Figure 46 A/D Mode Register 1 (AMR1)
59

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